Among the efforts for reducing the size of integrated circuits and reducing RC delay, three-dimensional integrated circuit (3DIC) and stacked dies are commonly used. Through-substrate vias (TSVs) are thus used in 3DIC and stacked dies. In this case, TSVs are often used to connect the integrated circuits on a die to the backside of the die. In addition, TSVs are also used to provide short grounding paths for grounding the integrated circuits through the backside of the die, which may be covered by a grounded metallic film.
There are two commonly used approaches for forming TSVs, via-first approach and via-last approach. When formed using the via-first approach, vias are formed before the back-end-of-line (BEOL) processes are performed. Accordingly, the TSVs are formed before the formation of metallization layers. Due to the thermal budget in the BEOL processes, however, the TSVs formed using the via-first approach suffer from problems such as copper popping and metal-1 to metal-2 bridging.
On the other hand, the via-last approach, although being cost effective and having a short time-to-market, the resulting structures are less efficient in power connection. For example, FIGS. 1 and 2 illustrate two interconnect structures comprising via-last TSVs. In FIG. 1, die 4 is bonded to die 2 through a face-to-face bonding. In FIG. 2, die 4 is bonded to die 2 through a face-to-back bonding. TSVs 6 are formed in dies 2, and are used for connecting power to the devices in dies 2. It is observed that regardless whether the power is introduced into die 2 from bump 12 as in FIG. 1, or introduced into die 2 from die 4 as in FIG. 2, the connection of the power to device 8 in dies 4 have long paths, as illustrated by arrows 14. Further, each of the long power paths 14 includes a plurality of metal lines and vias. Accordingly, the resistances of the power paths are also high.